1. Field of the Invention
The present invention relates generally to a high-speed ratio CMOS logic structure, and, more particularly, to such a logic structure that includes static and dynamic pullups/pulldowns employing feedback.
2. Description of the Related Art
A generalized understanding of CMOS logic structures may be had based on the assumption that p-channel, and n-channel MOS transistors act as simple switches. However, fundamental characteristics of such logic structures, such as the switching speed, the power dissipation, drive capability relative to subsequent stages and density restrictions have caused much investigation in the art as to the particular ways in which the MOS transistors deviate from the above-mentioned idealized viewpoint.
In particular, the above-mentioned drive requirement of a logic structure specifies that when an output of such structure should be a logic one, the output voltage should be as close to the positive power supply bus (e.g., V.sub.DD) as possible. Likewise, when the output of such a logic structure should be a logic low, the output voltage should be lower than the threshold voltage V.sub.t of the next stage in order to obtain proper logic results. However, to obtain such a result, switching speed is often compromised. In particular, design of a logic structure that satisfies the minimum and maximum output voltages necessarily involves assessing the relative pullup "strength", and pulldown "strength" of the pullup and pulldown paths that are commonly used to form such logic structures.
The "strength" of a pullup or pulldown path is measured generally by its ability to sink or source current. Typically, the stronger a path, the more current it can source or sink. Further, it is well-known that the current through a MOS device (i.e., thus the relative "strength") is a function of the MOS transistor gain factor .beta., and the voltage applied to the gate terminal relative to the source terminal (i.e., V.sub.gs). The transistor gain factor .beta. is further defined as a function of the process parameters, and device geometry. Thus, by manipulating V.sub.gs, and .beta. (in particular, relative device geometries such as channel width and length), the relative strength of the pullup and pulldown paths can be adjusted to obtain predetermined design criteria.
Referring now to FIG. 1, one approach in the prior art in the design of CMOS logic structures is known as a classic design ratio logic structure, shown particularly as a design ratio NOR logic gate 10. Gate 10 includes a pullup circuit defining a pullup path 12 implemented by a p-channel MOS (PMOS) device 14, a pulldown circuit defining a pulldown path 16, implemented using a plurality of n-channel MOS (NMOS) devices 18.sub.1, . . . , 18.sub.n-1, 18.sub.n, and output node 20. The relative strength of the pullup path 12 is defined, in part, by the reference voltage applied to the gate terminal of PMOS device 14. Further, for example, if the channel length of the PMOS device 14 (i.e., L.sub.p), and the NMOS devices 18.sub.i (i.e., L.sub.n) are assumed to be equal (i.e., L.sub.p =L.sub.n), then the pullup strength of path 12, as well as the pulldown strength through pulldown path 16 may also be controlled by varying the ratio (i.e., thus the so-called ratio design) of the channel width of the PMOS devices 14 (i.e., W.sub.p), and the channel width of the NMOS devices 18.sub.i (i.e., W.sub.n). Thus the pullup strength in the conventional design ratio NOR 10 may be defined by the magnitude of the reference voltage, and selection of particular device geometry. Likewise, the pulldown strength of circuit 16 may be defined as a function of the NMOS 18.sub.i device geometry. In any event, both the pullup and pulldown "strengths" are fixed.
In operation, the inputs (input 1, . . . , input n-1, input n) of NOR 10 may be connected to an output of a product term sense amplifier when NOR 10 is used in a programmable logic device (PLD). When any of the inputs, all of the inputs, or any combination of these inputs are high, the output DataOut on node 20 is driven low. Further, when all of the inputs are low, DataOut on output node 20 is driven high. This result is thus consistent with the logic NOR function.
To obtain these desired results, NOR gate 10 employs a ratio design between the referenced pullup device 14, and pulldown devices 18.sub.i. However, the ratio design, as discussed above, is constrained insofar as the pulldown strength must be sufficient to bring the potential on output node 20 to a level below threshold voltage V.sub.t of the next logic stage 22. It should also be apparent that if the pullup strength through pullup path 12 is too "strong", then one of the devices 18.sub.i may have insufficient "strength" to pull the DataOut on output node 20 to a sufficiently low potential state and will cause a speed penalty for a high-to-low transition of DataOut. However, if the pullup strength is too weak as compared to the pulldown strength, then the low-to-high transition will be affected.
Thus, a major disadvantage of the conventional design ratio logic structure, as shown by a NOR gate 10 embodiment in FIG. 1, is that the pullup and pulldown device strengths in that approach are fixed. The fixed strengths limit the switching speed of such a logic structure by the relative magnitude of the selected pullup and pulldown strengths.
Accordingly, there is a need to provide an improved logic structure, suitable for use in programmable logic devices (PLDs) or Complex Programmable Logic Devices (CPLDs) that minimizes or eliminates one or more of the problems as set forth above.